The present invention relates to data communication, and more particularly to communications between endpoint devices.
As computing and communications converge, the need for a common interconnect interface increases. Currently, significant resources are devoted to the development of costly, proprietary, customized solutions to enable these environments to interoperate and co-exist. Meanwhile, there is pressure to reduce time-to-market and cut development costs. To this end, a single commonly applied input/output (I/O) interface will likely become “standard” in the converging computing and communications environment.
Over time, computing has evolved around a single board-level interconnect (for example, the current de facto interconnect is the Peripheral Component Interconnect (PCI) in accordance with the PCI Specification, Rev. 2.1 (published Jun. 1, 1995)), while the communications industry has used many board-level and system-level interconnects, some proprietary, with others based on standards such as PCI. As the two areas converge, such different interconnect technologies create complexity in interoperability, coding, and physical design, all of which drive up costs. The use of fewer, common interconnects will simplify the convergence process and benefit infrastructure equipment developers.
Industry-standard interconnects that can be reused among multiple platforms aid in modular system design. Common chip-to-chip interconnects enable reuse of designs across boards, and improve interoperability between computing and communication functions. A common system fabric enables board-level modularity by standardizing the switching interfaces between various components of a modular system. Fewer, common interconnects also reduce complexity in software and hardware, and simplify system design.
The convergence trends of the compute and communications industries, along with inherent limitations of bus-based interconnect structures, has lead to the recent emergence of serial-based interconnect technologies. Serial interconnects reduce pin count, simplify board layout, and offer speed, scalability, reliability and flexibility not possible with parallel busses, such as PCI and PCI-X (in accordance with the PCI-X Specification, version 2.0 (published Jul. 22, 2002)) buses. These new technologies range from proprietary interconnects for core network routers and switches to standardized serial technologies, applicable to computing, embedded applications and communications.
One such standardized serial technology is the PCI Express™ architecture in accordance with the PCI Express™ Bus Specification, version 1.0a (published July 2002). The PCI Express™ architecture is targeted as the next-generation chip-to-chip interconnect for computing. In addition to providing a serial-based interconnect, the PCI Express™ architecture supports functionalities defined in the earlier PCI and PCI-X bus-based architectures. A need exists for extensions to the PCI Express™ architecture that enable greater convergence between compute and communications platforms, as well as enabling peer endpoints of such platforms to effectively communicate via a peer-to-peer protocol.